FIG. 1 is a circuit diagram of a conventional semiconductor memory device.
As shown, the semiconductor memory device includes a cell array 101, a bit line sense amplifier 102, a first connecting unit 103, a second connecting unit 104, a data bus sense amplifier 105, a writing driver 106, an input/output pad 107, first local lines SLO/SLOb, second local lines LIO/LIOb and a global line GIO. A plurality of resistors R1 to R4 are parasitic resistors loaded on the first and the second local lines SLO/SLOb and LIO/LIOb.
The cell array 101 includes word lines WL0 and WL1, bit lines BL and BLb and unit cells S1 and S2. The unit cells S1 and S2 are respectively arranged at the intersections of the word lines and the bit lines. If the word line WL0 is enabled, a data signal of the unit cell S2 is provided to the bit line BLb. If word line WL1 is activated, a data signal stored in the unit cell S1 is provided to the bit line BL and a predetermined reference signal is supplied to the bit line BLb.
The bit line sense amplifier 102 senses and amplifies signals of the bit lines BL and BLb. The first connecting unit 103 connects the bit lines BL and BLb to the first local lines SLO and SLOb, respectively according to YIT. The second connecting unit 104 connects the first local lines SLO and SLOb to the second local lines LIO and LIOb, respectively in response to SLOT. The data bus sense amplifier 105 senses and amplifies signals of the second local lines LIO and LIOb, and drives the global line GIO in response to the amplified signals. The signal supplied at the global line by the data bus sense amplifier 105 is output externally as data corresponding to a read command.
The writing driver 106 drivers the second local lines LIO and LIOb based on a data signal supplied at the global line GIO. The data signal supplied at the global line GIO is input received externally through the input/output pad 107.
Main operation of the semiconductor memory device includes a write operation and read operation. At the write operation, the semiconductor memory device stores a data unit provided from the external into a unit cell selected by an address input with the data. At the read operation, the semiconductor memory device outputs a data unit selected by an address of read operation into the external.
At the writing operation, a selected word line, e.g., WL1 is activated and a data signal stored at the unit cell S1 is provided to the bit line BL. The sense amplifier 102 senses, amplifies, and latches the data signal of the bit line BL. An input data signal is transferred to the global line GIO through the input/output pad 107. The writing driver 106 drives the second local lines LIO and LIOb based on the input data signal supplied at the global line GIO. Since the first connecting unit 103 and the second connecting unit 104 are enabled during the writing operation, the input data signal is transferred to the bit line sense amplifier 102 through the local lines LIO/LIOb and SIO/SIOb. If the input data signal is different from the data signal latched by the sense amplifier 102, the bit line sense amplifier 102 removes the latched data signal and newly latches the input data signal. The input data signal newly latched by the bit line sense amplifier 102 is stored at the unit cell S1.
The read operation is similar to the write operation except that the data bus sense amplifier 105 is used instead of the writing driver 106 and the direction that data signal moves is reverse. Thus, description of the read operation is omitted.
FIG. 2 is a schematic circuit diagram of a writing driver in FIG. 1.
As shown, the writing driver 106 includes a first data transferring unit 106A, a second data transferring unit 106B, a first writing driver 106C, and a second writing driver 106D. The first data transferring unit 106A receives and latches a signal based on a data signal supplied at the global data line GIO in response to a reset signal LIORSTb and an enable signal BWEN. The second data transferring unit 106B receives and latches a signal based on an inverted signal of the data signal supplied at the global data line GIO in response to the reset signal LIORSTb and the enable signal BWEN. The first writing driver 106C pulls up or pulls down the second local line LIO using the signal latched by the first data transferring unit 106A and the signal latched by the second data transferring unit 106B. The first writing driver 106D pulls up or pulls down the second local line LIOb using the signal latched by the first data transferring unit 106A and the signal latched by the second data transferring unit 106B.
If the reset signal LIORSTb is a logic low level, PMOS transistors P1 and P3 are turned on. Outputs of latches L1 and L2 are respectively a logic low level. Then, MOS transistors P2, P4, N3 and N6 are turned off.
If the reset signal LIORSTb is a logic high level and the enable signal BWEN is a logic high level, MOS transistors N1 and N4 are turned on and MOS transistors P1 and P3 are turned off. Assume that an input data signal of the write operation is logic high level. Then, MOS transistor N2 is turned on and the latch L1 of the first data transferring unit 106A latches and outputs a signal having a logic high level. Alternatively, MOS transistors N5 are turned off and the latch L4 of the second data transferring unit 106B latches and outputs a signal having a logic low level. Thus, the MOS transistors P2 and N6 are turned off and the MOS transistors N3 and P4 are turned on. The second local line LIO is pulled down as a level of a core voltage VCORE and the second local line LIOb is pulled up as a level of a ground voltage VSS.
To reduce power consumption, the semiconductor memory device uses the core voltage VCORE that is lower than the external power supply voltage as an operating voltage at a core area. Thus, the first writing driver 106C drives the second local line LIO as a pull-up level of the core voltage VCORE. The second writing driver 106D drives the second local line LIOb as a pull-up level of the core voltage VCORE.
However, because of parasitic resistance on the local lines LIO/LIOb and SIO/SIOb, it takes too much time to transfer a data signal from the writing driver into a unit cell. That is, the data writing time of the semiconductor memory device is too long.